The present invention relates to a double integration or dual slope, delta-sigma, analog-digital coder. The invention applies to the coding of signals and more particularly to the transmission of signals on communications channels of the PCM type (pulse code modulation). It also applies to the measurement of d.c. voltages.
Circuits integrated on a substrate and particularly digital signal processing circuits are appearing in increasing numbers and with ever-greater complexity. The quality of the processing of the signal obtained as a result of these circuits, as well as the technical performances (size of the circuits, low dissipated power, reliability, etc.) make it possible to continuously envisage new uses of these circuits in fields which, hitherto have been reserved for analog circuits. However, there is at present a difficult to solve problem caused by the interface between the analog part and the digital part of a functional assembly. Although digital processing techniques have evolved very rapidly, this does not apply to analog-digital interfaces.
In most cases, the integration of a circuit of conventional analog-digital coder components is a very costly solution, it being very difficult to apply large-scale integration methods thereto.
This difficulty is overcome by using an analog-digital coder "with shaping of the noise spectrum", such as a delta-sigma coder. Such a coder is more particularly described in the article by Tewksbury and Hallock entitled "Oversampled, linear predictive and noise-shaping coders of order N&gt;1", which appeared in the Journal "IEEE Transactions on Circuit and System", Vol. CAS-25, No. 7, July 1978. Such a coder is also described in U.S. Pat. No. 4,301,446. Delta-sigma noise spectrum shaping coders make it possible to reduce to the minimum the number of elements having to operate under linear conditions and which carry out most of the digital processing operations. The interest of these coders is that they make it possible to benefit to the maximum from the integration techniques of digital circuits. The analog part can be produced from discrete elements, or integrated on an additional analog circuit, or can even be directly integrated into the digital processing circuit if the technology permits. Another advantage of such coders is that when they use a quantization on a single bit for the digital conversion, they are relatively insensitive to transmission disturbances in a very noisy environment, e.g. an industrial environment. The noise spectrum shaping principle used in these coders ensures that they perform very well in the measurement of low-power d.c. voltages.
Double integration delta-sigma analog-digital coders are special coders, whose structure and operating principle are directly derived from the structure and operation of noise spectrum shaping coders.
The principle of a noise spectrum shaping coder has long been known and a very detailed study thereof is given in the above-cited article by Tewksbury et al.
FIG. 1 diagrammatically shows a noise shaping coder, which comprises adders 1, 2 and a quantizer 3, which makes it possible to sample an input signal E(Z) at a frequency F.sub.ech. It also comprises a feedback filter B(Z) and a negative feedback filter C(Z) in a feedback loop connecting the output of the coder to one of the inputs of adder 1. The output signal is designated Q(Z), whilst N(Z) represents the noise which is inherent in any analog-digital converter and appears during any quantization operation in such a conversion type. It is assumed that the input signal E(Z) has already been sampled at frequency F.sub.ech and hereinafter the state variable Z is used for representing the different signals.
It is known that the quantization noise N(Z) decreases as quantization becomes finer, i.e. when the number of bits at the output of the decoder is higher. Of interest in this coder is that it can operate with a very rough quantization. The remainder of the description only deals with two-level quantizers (one bit).
The output signal Q(Z) of the coder is easily expressed on the basis of F(Z) and N(Z) in the following way: EQU Q(Z)=B(Z).multidot.(E(Z)-Q(Z).multidot.C(Z))+N(Z) EQU Q(Z)=E(Z).multidot.B(Z)/(1+B(Z).multidot.C(Z)+N(Z)/(1+B(Z).multidot.C(Z))
B(Z) and C(Z) representing the transfer functions of the feedback and negative feedback filters.
It is said that a noise shaping coder is obtained when B(Z) and C(Z) satisfy the following equations: EQU B(Z)/(1+B(Z).multidot.C(Z))=Z.sup.-P (pure phase shifter) EQU 1+B(Z).multidot.C(Z)=H(Z)
It has been shown, particularly in the aforementioned Tewksbury and Hallock article, that a function B(Z) of from 1/(1-Z.sup.-1).sup.n relative to an nth order digital integrator minimizes the noise in a signal frequency band B (extending from zero to B). When this function is involved, the noise spectrum shaping coder is then a delta-sigma coder, whose order is given by the power n of the function B(Z).
FIG. 2 diagrammatically shows a first-order delta-sigma coder. This coder is also described in the aforementioned article and comprises an adder 4 receiving at its input an already sampled signal E(Z) and which receives at another input the output signal Q(Z). This coder also comprises an integrator 5 constituted in per se known manner by an operational amplifier circuit. The output of this integrator is connected to the input of a quantizer 6, which receives a sampling signal at a frequency F.sub.ech at a control input. In the case of this first order noise shaping coder, we obtain: EQU B(Z)=Z.sup.-1 /(1-Z.sup.-1)
in which B(Z) is the Z transfer function of an integrator associated with zero order 0 blocker. In this case, C(Z)=1, so that: EQU Q(Z)=Z.sup.-1 .multidot.E(Z)+(1-Z.sup.-1)Q.sup.Z.
On abstracting Z.sup.-1 .times.E(Z) corresponding to a simple delay, in this relation, we obtain an equation of form H(Z)=1+B(Z).multidot.C(Z), as referred to hereinbefore.
The use of delta-sigma coders as the sampler in an analog-PCM converter has already been proposed in the article "A single channel PCM coder" by J. D. EVERARD, IEEE, ICC 1978, Toronto, June 1978.
The sampling frequency is 2.048 MHz for the coder described in that article. Such a frequency does not make it possible to obtain the signal-to-noise ratio imposed by the standards, particularly at low levels. It has already been proposed (cf. "Improvements to delta-sigma modulators when used for PCM encoding" by J. D. EVERARD in Electronics Letters, July 22, 1976, Vol.12, No.15, p.379) to increase the signal-to-noise ratio at low levels by injecting a spurious signal at a frequency such that it is filtered by the digital undersampling filter. Such a process increases the signal-to-noise ratio at low levels, but decreases it at high levels.
The construction of second-order (or double integration) delta-sigma coder has already been proposed in the aforementioned U.S. Pat. No. 4,301,466 in which the coder is applied to a transmission channel by modulations of coded pulses and the feedback and negative feedbacks used by it are essentially based on digital technology. The realization of this coder has taken place following a comparative study of various first-order delta-sigma coders using digital technology. These coders are more particularly described in the article "A single PCM Codec" by EVERARD, IEEE Journal of Solid State Circuits, Vol. SC-14, Feb. 1, 1979, as well as in the article "Single-Chip per channel Codec with filters utilizing delta-sigma modulations", by MISAWA, INERSEN, LOPORCADRO and RUCH, IEEE Journal of Solid State Circuits, Vol. SC-16, Aug. 4, 1981.
The investigation of these various constructions shows that the performances reached are inadequate to enable the transmission systems using such coders to correctly conform to the standards laid down by CCITT and in particular notice G712 thereof.
FIG. 3 is a circuit diagram of a known double integration delta-sigma coder, such as described in U.S. Pat. No. 4,301,446. The delta-sigma coder shown comprises a first adder 10 and a second adder 11. Adder 10 firstly receives input signal E(Z) and secondly receives output signal Q(Z) from the coder. The output of this first adder is connected to the input of a first integrator 12, whose output is connected to an input of the second adder 11, which receives the output signal Q(Z) from the coder across a second-order (multiplier by 2) recursive negative feedback filter 13. The output of the second adder 11 is connected to one input of a second integrator 14. Finally, the output of the second integrator is connected to an input of a quantization circuit 15, controlled by a sampling signal having a sampling frequency F.sub.ech. The output of this sampling circuit constitutes the output of the double integration delta-sigma coder. This transfer function is of form ##EQU1## as indicated in the aforementioned patent. In this relation, .epsilon.=1/F.sub.ech designates the sampling cycle or period.
A construction of a second-order delta-sigma coder only using a single operational amplifier is described in U.S. Pat. No. 4,301,446. This coder is diagramamtically shown in FIG. 4 and its transfer function is as follows: ##EQU2## by setting G=-16(R/R.sub.1).tau.=1/f.sub.ech =4RC.
The double integration delta-sigma coder shown in FIG. 4 comprises an operational amplifier 20 with, in its negative feedback channel, a cell formed by two series-connected capacitors 21, 22 of capacitance C and a parallel resistor 23 of value R. The output of the operational amplifier is connected to two flip-flops 24, 25 in cascade and the outputs thereof are connected to the input of the operational amplifier 20 by resistors 26, 27 of respective resistance R' and 2R'. The resistance of resistor 27 is double that of resistor 26 in order to obtain a binomial coder. The two flip-flops 24, 25 associated with the resistors 26, 27 realize the transfer function EQU C(z)=2-z.sup.-1
The output of the second flip-flop is on Q.
Experience has shown that on choosing R'=R.sub.1 (R.sub.1 being the resistance of input resistor 28), the voltage of the second-order filter reaches excessively high values, which can cause blocks. To obviate this disadvantage, EQU C(z)=2-z.sup.-1,
is replaced by EQU C(z)=2(2-z.sup.-1).
In FIG. 4, F.sub.ech represents the sampling frequency of the sampling signals applied to the input C of the type D flip-flops 24, 25, while +V.sub.ref and -V.sub.ref represent the reference voltages applied to these flip-flops. This arrangement is very sensitive to noise and the value of the components used therein makes it difficult to integrate.